GAAS-MESFET DIFFERENTIAL PASS-TRANSISTOR LOGIC

A GaAs MESFET implementation of differential passtransistor logic (DPTL) is presented. This logic technique combines the greater area efficiencies and high operation speeds of ratioless, pass-transistor circuits with the additional advantages of good noise immunity and low power dissipation. Experimental results are provided for a four-bit counter implemented in a 1μm, depletion (D)-mode MESFET technology to demonstrate both the functionality and noise immunity of GaAs DPTL. © 1990, The Institution of Electrical Engineers. All rights reserved.