A COMPILER-ASSISTED SCHEME FOR ADAPTIVE CACHE COHERENCE ENFORCEMENT

被引:0
作者
NGUYEN, TN [1 ]
MOUNESTOUSSI, F [1 ]
LILJA, DJ [1 ]
LI, ZY [1 ]
机构
[1] UNIV MINNESOTA,DEPT ELECT ENGN,MINNEAPOLIS,MN 55455
来源
PARALLEL ARCHITECTURES AND COMPILATION TECHNIQUES | 1994年 / 50卷
关键词
PERFORMANCE ANALYSIS AND DESIGN AIDS; MULTIPLE DATA STREAM ARCHITECTURES (MULTIPROCESSORS); LARGE AND MEDIUM (MAINFRAME) COMPUTERS;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Cache coherence mechanisms in shared-memory multiprocessors typically use either updating or invalidating to prevent access to stale data, but neither enforcement strategy is the best choice for all programs. We present a compile-time optimization that uses the look-ahead capability of the compiler to select updating, invalidating, or neither for each write reference in a program to thereby produce the best overall memory performance. We implement this optimization in the Parafrase-2 compiler for memory references to scalar variables and use trace-driven simulations to compare the performance of this compiler-assisted adaptive coherence enforcement to hardware-only mechanisms. We find that this compiler optimization can produce miss ratios comparable to those produced by an updating-only mechanism while frequently reducing the total network traffic to below that produced by any of the hardware-only mechanisms.
引用
收藏
页码:69 / 78
页数:10
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