HIGH-PERFORMANCE BIT-SERIAL ADDERS AND MULTIPLIERS

被引：2

作者：

BI, G ^{[1
]}

JONES, EV ^{[1
]}

机构：

[1] UNIV ESSEX,DEPT ELECTR SYST ENGN,COLCHESTER CO4 3SQ,ESSEX,ENGLAND

来源：

IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS | 1992年 / 139卷 / 01期

关键词：

ADDER; BIT-SERIAL PROCESSING; MULTIPLIER; PIPELINED STRUCTURES; SYSTOLIC ARRAYS;

D O I：

10.1049/ip-g-2.1992.0018

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design methodology is presented which uses clocked logic modules to synthesise flexible high performance multipliers. By using two-stage pipelined bit-serial adders, a bit-serial multiplier can be designed which is capable of producing both single- and double-precision products for continuous two's complement data streams. High processing speeds are possible owing to the systolic structure which is pipelined at the gate level.

引用

页码：109 / 113

页数：5

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