VLSI IMPLEMENTATION OF DIGIT-SERIAL ARITHMETIC MODULES

被引：1

作者：

BISDOUNIS, L

METAFAS, DE

MARAS, AM

MAVRIDIS, C

机构：

[1] UNIV PATRAS,DEPT ELECT ENGN,VLSI DESIGN LAB,GR-26110 PATRAI,GREECE

[2] UNIV CRETE,DEPT ELECTR & COMP ENGN,GR-73100 KHANIA,GREECE

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1993年 / 39卷 / 2-5期

关键词：

D O I：

10.1016/0165-6074(93)90099-7

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This article describes an implementation of arithmetic modules which is based on the transmission of arithmetic data serially one digit at a time. For some applications bit-serial architectures may be too slow, and bit-parallel architectures may be faster than necessary and require too much hardware. The desired sample rate in these applications can be achieved using the digit-serial approach.

引用

页码：251 / 254

页数：4

共 7 条

[1] Denyer, Renshaw, VLSI Signal Processing, A Bit-Serial Approach, (1985)
[2] Hatamian, Cash, Parallel bit-level pipelined VLSI designs for high speed signal processing, Proceedings of the IEEE, 75, pp. 1192-1202, (1987)
[3] Hartley, Corbett, Digit-Serial Processing Techniques, IEEE Trans. on Circuits and Systems, 37, 6, pp. 707-719, (1990)
[4] Parhi, A Systematic Approach for Design of Digit-Serial Signal Processing Architectures, IEEE Trans. on Circuits and Systems, 38, 4, pp. 51-58, (1991)
[5] Ait-Boudaoud, KIbrahim, Hayes, Novel cell architecture for bit level systolic arrays multiplication, Proc. IEE, 138, pp. 21-26, (1991)
[6] Hwang, Computer Arithmetic: Principles, Architectures and Design, (1979)
[7] Montuschi, Mezzalama, Survey of square rooting algorithms, Proc. IEE, 137, pp. 31-40, (1990)

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