CARRIER MOBILITY IN SILICON MOSTS

The mobility and density of free carriers in surface channels have been obtained from conductivity and Hall measurements performed on large experimental silicon MOST's. Uniform n- and p-type channels, with various crystallographic orientations have been studied over a range of temperatures, gate biases, and reverse biases between the channel and substrate. No trapping of induced carriers has been observed when the gate voltage is more than a few volts above threshold. The mobility of free carriers is very small at threshold. It increases rapidly with gate voltage and shows a maximum of about 1 3 or 1 2 of its bulk value, at gate voltages corresponding to free carrier densities of about 2-7 × 1011 carriers/cm2. At larger gate voltages the mobility shows a slow decrease. The mobility is also affected by bias between channel and substrate. A hysteresis in channel conductance is observed at room temperature. It is shown that a hysteresis in carrier mobility contributes appreciably to this effect. Finally, it is demonstrated by means of an example that the variations of mobility with gate and substrate bias have an appreciable influence on the drain characteristics of MOST's. © 1969.