A GENERIC HARDWARE ARCHITECTURE TO SUPPORT THE SYSTEM-LEVEL SYNTHESIS OF DIGITAL-SYSTEMS

A generic hardware architecture, which is the target for a system level VLSI synthesis system, is described in this paper. The specification of a real-time control system is defined, in the language BEADLE, as a logical network of concurrently active sequential tasks, which synchronise in order to communicate. The architecture was designed to implement such specifications using a number of node processors - one per task - interconnected via a customised communications network. The novelty of this approach is that the generic architecture is personalised by a high-level synthesis system for an application. The resulting hardware architecture is defined in VHDL, and is used as an input to lower-level physical synthesis tools. The relationship between the BEADLE language and the generic architecture is described, together with details of how the architecture is customised for specific applications. A critical appraisal of the prototype architecture is presented and future directions discussed.