NEUROCHIPS WITH ON-CHIP BACKPROPAGATION AND/OR HEBBIAN LEARNING

被引：44
作者：
SHIMA, T
KIMURA, T
KAMATANI, Y
ITAKURA, T
FUJITA, Y
IIDA, T
机构：
[1] TOSHIBA CO LTD,CTR SEMICOND SYST ENGN,SAIWAI KU,KAWASAKI 210,JAPAN
[2] TOSHIBA CO LTD,DIV KLIN RADIOL,KAWASAKI 210,JAPAN
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 12期
关键词：
D O I：
10.1109/4.173117
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A layered neural net is realized with two chips. One chip implements 24 x 24 synapses, a local weight control mechanism, and quantized +/- 1 LSB, both momentum and weight update scheme. The other contains 24 neurons, implementing not only backward propagation (BP) but Hebbian learning, with 200-pF drive capability. Some experimental chip characteristics are observed to verify implemented techniques.
引用
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页码：1868 / 1876
页数：9
相关论文
共 23 条
[1]  
AMARI S, 1978, MATH PRINCIPLES NEUR
[2]  
[Anonymous], 1987, LEARNING INTERNAL RE
[3]   EEPROM SYNAPSES EXHIBITING PSEUDO-HEBBIAN PLASTICITY [J].
CARD, HC ;
MOORE, WR .
ELECTRONICS LETTERS, 1989, 25 (12) :805-806
[4]  
COLLINS DR, 1989, P IEEE INT S CIRC SY, P834
[5]   CHARACTERISTICS OF FLOATING GATE DEVICE AS ANALOG MEMORY FOR NEURAL NETWORKS [J].
FUJITA, O ;
AMEMIYA, Y ;
IWATA, A .
ELECTRONICS LETTERS, 1991, 27 (11) :924-926
[6]  
FURMAN B, 1988, 22ND P AS C SIGN SYS
[7]  
GRIFFIN M, 1991, ISSCC DIG TECH PAPER, P180
[8]  
HOLLER M, 1988, JUN P INT JOINT C NE, P191
[9]   HIGH-SPEED CMOS I/O BUFFER CIRCUITS [J].
ISHIBE, M ;
OTAKA, S ;
TAKEDA, J ;
TANAKA, S ;
TOYOSHIMA, Y ;
TAKATSUKA, S ;
SHIMIZU, S .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1992, 27 (04) :671-673
[10]  
LINSKER R, 1988, IEEE COMPUT, V21, P105, DOI DOI 10.1109/2.36
123