A HARDWARE LOGIC SIMULATION SYSTEM

Hardware simulators are becoming increasingly common in today's VLSI design environments. Earlier, we described the architecture and design of one such hardware accelerator, microprogrammable accelerator for rapid simulations (MARS) [1], [2]. In this paper, we focus on multiple delay logic simulation algorithms developed for MARS. In particular, timing analyses algorithms for event cancellations, spike and race analyses, and oscillation detection are described in detail. We demonstrate how a reconfigurable set of processors, called processing elements (PE's) can be arranged in a pipelined configuration to implement these algorithms. The algorithms operate within the partitioned memory, message-passing architecture of MARS. We have implemented three logic simulators— two multiple delay and one unit delay— using slightly different configuration of the available PE's. In these simulators, VLSI chips are modeled at the gate level with accurate rise/fall delays assigned to each logic primitive. On-chip memory blocks are modeled functionally and are integrated into the simulation framework. The MARS hardware simulator has been tested on many VLSI chip designs and has demonstrated a speed improvement of about 50 times an Amdahl 5870 system running a production quality software simulator while retaining the accuracy of simulations. © 1990 IEEE