TRAFFIC MANAGEMENT CIRCUIT FOR THE SHARED BUFFER MEMORY SWITCH WITH MULTICASTING

被引：0
作者：
WU, JS
KUO, FJ
机构：
[1] Department of Electrical Engineering, National Central University, Chung-Li
来源：
COMPUTER COMMUNICATIONS | 1993年 / 16卷 / 11期
关键词：
TRAFFIC MANAGEMENT; SHARED BUFFER MEMORY SWITCH; MULTICASTING;
D O I：
10.1016/0140-3664(93)90075-4
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
The shared buffer memory switch has some merits such as higher bandwidth utilization and lower buffer size. It can also be modified to perform multicasting, but the multicasting cells have a higher priority to be switched. The traffic management circuit (TMC) we propose in this paper can solve this unfair problem by properly allocating the throughputs of both multicasting and general cells. The formulae for setting the control parameter in TMC are also derived.
引用
收藏
页码：736 / 739
页数：4
相关论文
共 6 条
[1]  
HUI J, 1987, P INT C COMM IEEE, P782
[2]   32X32 SHARED BUFFER TYPE ATM SWITCH VLSIS FOR B-ISDNS [J].
KOZAKI, T ;
ENDO, N ;
SAKURAI, Y ;
MATSUBARA, O ;
MIZUKAMI, M ;
ASANO, K .
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1991, 9 (08) :1239-1247
[3]  
KUWAHARA H, 1989, P ICC 89, P118
[4]   LARGE-SCALE ATM MULTISTAGE SWITCHING NETWORK WITH SHARED BUFFER MEMORY SWITCHES [J].
SAKURAI, Y ;
IDO, N ;
GOHARA, S ;
ENDO, N .
IEEE COMMUNICATIONS MAGAZINE, 1991, 29 (01) :90-96
[5]   A ONE-CHIP SCALABLE 8-STAR-8 ATM SWITCH LSI EMPLOYING SHARED BUFFER ARCHITECTURE [J].
SHOBATAKE, Y ;
MOTOYAMA, M ;
SHOBATAKE, E ;
KAMITAKE, T ;
SHIMIZU, S ;
NODA, M ;
SAKAUE, K .
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 1991, 9 (08) :1248-1254
[6]   FAST PACKET SWITCH ARCHITECTURES FOR BROAD-BAND INTEGRATED SERVICES DIGITAL NETWORKS [J].
TOBAGI, FA .
PROCEEDINGS OF THE IEEE, 1990, 78 (01) :133-167
1