TIME EFFICIENT SYSTOLIC ARCHITECTURE FOR MATRIX-STAR-VECTOR MULTIPLICATION

被引：0
|
作者：
ZUBAIR, M [1 ]
MADAN, BB [1 ]
机构：
[1] USN,POSTGRAD SCH,DEPT ELECT & COMP ENGN,MONTEREY,CA 93943
来源：
INFORMATION PROCESSING LETTERS | 1987年 / 24卷 / 04期
关键词：
D O I：
10.1016/0020-0190(87)90138-4
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
SIGNAL PROCESSING
引用
收藏
页码：225 / 231
页数：7
相关论文
共 50 条
  • [1] FAST LINEAR SYSTOLIC MATRIX VECTOR MULTIPLICATION
    GUSEV, M
    EVANS, DJ
    TASIC, J
    INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS, 1992, 43 (3-4) : 231 - 248
  • [2] Efficient Sparse Matrix-Vector Multiplication on Intel PIUMA Architecture
    Aananthakrishnan, Sriram
    Pawlowski, Robert
    Fryman, Joshua
    Hur, Ibrahim
    2020 IEEE HIGH PERFORMANCE EXTREME COMPUTING CONFERENCE (HPEC), 2020,
  • [3] New systolic modular multiplication architecture for efficient Montgomery multiplication
    Choi, Se-Hyu
    Lee, Keon-Jik
    IEICE ELECTRONICS EXPRESS, 2015, 12 (02):
  • [4] Design and Evaluation of a Power-Efficient Approximate Systolic Array Architecture for Matrix Multiplication
    Waris, Haroon
    Wang, Chenghua
    Li, Weiqiang
    Lombardi, Fabrizio
    PROCEEDINGS OF THE 2019 IEEE INTERNATIONAL WORKSHOP ON SIGNAL PROCESSING SYSTEMS (SIPS 2019), 2019, : 13 - 18
  • [5] A REUSABLE SYSTOLIC ARRAY FOR MATRIX-VECTOR MULTIPLICATION
    EVANS, DJ
    MARGARITIS, KG
    INTERNATIONAL JOURNAL OF COMPUTER MATHEMATICS, 1991, 41 (1-2) : 19 - 30
  • [6] A family of bidirectional systolic arrays for matrix-vector multiplication
    Milovanovic, IZ
    Milovanovic, EI
    Tokic, TI
    Stojanovic, NM
    Stojcev, MK
    MODERN PROBLEMS OF RADIO ENGINEERING, TELECOMMUNICATIONS AND COMPUTER SCIENCE, PROCEEDINGS, 2002, : 90 - 92
  • [7] SYSTOLIC MATRIX AND VECTOR MULTIPLICATION METHODS FOR SIGNAL-PROCESSING
    URQUHART, RB
    WOOD, D
    IEE PROCEEDINGS-F RADAR AND SIGNAL PROCESSING, 1984, 131 (06) : 623 - 631
  • [8] Synthesis of a unidirectional systolic array for matrix-vector multiplication
    Milovanovic, IZ
    Milovanovic, EI
    Bekakos, MP
    MATHEMATICAL AND COMPUTER MODELLING, 2006, 43 (5-6) : 612 - 619
  • [9] Systolic Architecture for Integer Point Matrix Multiplication using FPGA
    Sonawane, D. N.
    Sutaone, M. S.
    Malek, Inayat
    ICIEA: 2009 4TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-6, 2009, : 3813 - +
  • [10] Designing of processor-time optimal systolic arrays for band matrix-vector multiplication
    Milovanovic, IZ
    Milovanovic, EI
    Milentijevic, IZ
    Stojcev, MK
    COMPUTERS & MATHEMATICS WITH APPLICATIONS, 1996, 32 (02) : 21 - 31
12345