A CHIP SET CORE FOR IMAGE COMPRESSION

被引：5

作者：

ARTIERI, A

COLAVIN, O

机构：

[1] SGS-Thomson Microelectronics, Image Processing Business Unit, 38019, Grenoble, Cedex, 17

来源：

IEEE TRANSACTIONS ON CONSUMER ELECTRONICS | 1990年 / 36卷 / 03期

关键词：

D O I：

10.1109/30.103150

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Todays efficient codecs for full motion image compression are based on two key functions: Discrete Cosine Transform (DCT) and Motion Estimation. This fact is strongly supported by international standardization committees (ISO, CCITT) that are currently standardizing techniques for compression of pictures (still and moving) based on DCT and Motion Compensation. Two new components performing these functions are presented. The first component computes 8*8 Discrete Cosine Transform and zig zag conversion of coefficient scanning for a pixel rate up to 27 Mhz. The second component computes full search Motion Estimation for a pixel rate up to 18 Mhz. System implementation for image compression is then discussed. © 1990 IEEE

引用

页码：395 / 402

页数：8