CLOCK PERIOD MINIMIZATION WITH WAVE PIPELINING

In a design where clock arrival times at the flipflops are equalized, the delay along the maximum logic path imposes a lower bound on the clock period. It is possible to further minimize the clock period by introducing controlled clock signal delays at the flipflops. The introduction of these delays allows multiple signal waves, related to different clock cycles, to propagate simultaneously on logic paths during operation. A form of wave pipelining takes place in the logic. A linear program is formulated for clock period minimization under single phase clocking schemes. Edge triggered flipflops are used as the circuit memory elements, and controlled delays are introduced in the clock signal arrival times at these elements. Constraints are derived that relate the logic path delays from pairs of input flipflops. These constraints, in addition to known constraints relating input and output flipflops, prevent destructive logic signal propagation interference. It is shown that in circuits without feedback the clock period reduction is limited by the shortest paths in the logic and the required signal separation between signals of distinct cycles. Application of this technique to logic with feedback is discussed.