ELECTRICAL MECHANISM FOR HOLDING TIME DEGRADATION IN DYNAMIC MOS RAMS

被引:12
作者
FURUYAMA, T
OHUCHI, K
KOHYAMA, S
机构
[1] Semiconductor Device Engineering Laboratory, Toshiba Corporation, Kawaeaki
关键词
D O I
10.1109/T-ED.1979.19672
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Holding time degradation due to electrically generated excess minority carriers has been observed in a 16-kbit dynamic MUS RAM. The failure mode is described by two-step impact ionization in a drain depletion region of a transistor and a subsequent diffusion process. Other experiments by a dynamic MOS RAM cell test device, a charge-coupled device, and a He-Ne laser for carrier excitation, consistently verify the mechanism which leads to degradation of stored information. In addition, the actual failure map is successfully reproduced by an optical experiment, and also in a computer simulation. Effects of electrical excess minority-carrier generation are discussed from a reliability point of view, particularly for dynamic MOS LSI's. Copyright © 1979 by The Institute of Electrical and Electronics Engineers, Inc.
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页码:1684 / 1690
页数:7
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