A MULTITHREADED PROCESSOR ARCHITECTURE WITH SIMULTANEOUS INSTRUCTION ISSUING

In this paper, we propose a multithreaded architecture which can improve machine throughput. In this architecture, an instruction from one thread is issued simultaneously with instructions from other threads, and these instructions can begin execution unless they are competing with one another for the same functional unit. Our architecture also makes it possible to parallelize a still wider range of loops than on vector or VLIW machines. Simulation results show that a 1.9 and a 2.8 times speed-up can be gained by permitting, respectively, two and four independent instruction streams to be executed on a processor.