VLSI ARCHITECTURES FOR HIGH-SPEED AND FLEXIBLE 2-DIMENSIONAL DIGITAL-FILTERS

High-speed two-dimensional (2-D) digital filters are important in many practical signal-processing applications. This paper describes flexible VLSI architectures for high-speed 2-D FIR and IIR digital filters. Cyclical parallel processing structures for 2-D FIR and IIR digital filtering are first derived from the employment of storage elements. The hardware architectures that realize the parallel processing structures are then developed. The resulting architectures, which are mainly constructured of three types of standard cells, exhibit a high degree of modularity and regularity, and thus a high suitability for VLSI implementation. The proposed architectures can process 2-D data arrays of arbitrary dimensions in real time or near real time, and have higher hardware efficiency and lower implementation cost than the direct form realization.