Design and Performance Analysis of Current Starved VCO for PLL Using SVL Technique

In the recent electronics, integrated circuits have been designed using complementary metal oxide semiconductor (CMOS). In 1963, Frank Wanlass at Fairchild technologies first examined the logic gate using CMOS VLSI [1]. With the improvement of Integrated Circuit ( IC) technologies, communication systems and microprocessors are mainly operating at several gigahertz frequencies with low power, small chip area and an agreeable cost [2]. Nowadays is communications craving, requiring faster and more dependable ways to give an information flow. Voltage Controlled Oscillator finds expansive applications in many areas such as communication systems, wireless systems, digital circuits and power systems [3]. It is to designs an output signal which oscillates at the similar frequency as the input signal. The design is implemented in cadence virtuoso tool in 45nm CMOS technology at 0.7V power supply. Measured performances shows that leakage current, noise and power consumption in SVL technique is reduced as current starved voltage controlled oscillator.