ANALOG CMOS CONTINUOUS-TIME TAPPED DELAY-LINE CIRCUIT

被引：0

作者：

JUSTH, EW ^{[1
]}

KUB, FJ ^{[1
]}

机构：

[1] USN,RES LAB,WASHINGTON,DC 20375

来源：

ELECTRONICS LETTERS | 1995年 / 31卷 / 21期

关键词：

ANALOG CIRCUITS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DELAY LINES;

D O I：

10.1049/el:19951285

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A microelectronic 20-stage tapped delay line consisting of cascaded lowpass filter amplifier stages has been demonstrated. The delay per tap is similar to 2.7ns, and different versions have been optimised for pulsed and narrowband operation in the 30 - 70 MHz frequency range. Potential applications are in radar and adaptive antenna systems.

引用

页码：1793 / 1794

页数：2

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