TEMPORAL LOGIC PROGRAMMING FOR ASSEMBLY SEQUENCE PLANNING

被引:9
作者
SEOW, KT [1 ]
DEVANATHAN, R [1 ]
机构
[1] NANYANG TECHNOL UNIV,SCH ELECT & ELECTR ENGN,DIV INSTRUMENTAT & CONTROL,SINGAPORE 2263,SINGAPORE
来源
ARTIFICIAL INTELLIGENCE IN ENGINEERING | 1993年 / 8卷 / 04期
关键词
ASSEMBLY SEQUENCE PLANNING; KNOWLEDGE REPRESENTATION AND REASONING; LOGIC PROGRAMMING; TEMPORAL LOGIC; CONSTRAINT; STATE-GRAPH;
D O I
10.1016/0954-1810(93)90008-4
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
A temporal-constraint logic programming framework for the specification and automatic verification and synthesis of assembly sequences is developed. The implemented tool is based on the formulated and derived precedence properties for a general mechanical assembly. This tool, called the Mechanical Assembly Sequence Satisfiability Checker (MASS-C), supports the use of a subset of temporal logic for assembly constraint specification. MASS-C provides the logic programming framework by which the designer can be relieved of the tedium of finding the assembly sequences, and the assembly sequence planning process manifests itself in the implicit modelling of assembly sequences by acquiring and formulating the set of correct and complete assembly constraints as a logic program. MASS-C implements a class of temporal expressions as predicates for logic programming of assembly constraints. It provides facilities to either verify an assembly sequence or synthesise all assembly sequences that satisfy the specified constraints composed as a logic program. Two examples illustrate the use of MASS-C for such verification and synthesis.
引用
收藏
页码:253 / 263
页数:11
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