AN ARCHITECTURAL MODEL FOR OR-PARALLELLISM ON DISTRIBUTED MEMORY-SYSTEMS

A model for OR-parallel execution of logic programs on highly parallel, distributed memory architectures is proposed. The model aims to reduce the overhead due to a parallel execution by using a parallel decomposition of a WAM into three units devoted to, respectively, memory management, unification, and subtree scheduling. A further unit may be introduced to handle message routing in the case of partial interconnection networks. The proposed model can be applied independently of the method to handle the multiple bindings for a variable. After discussing the parallel decomposition of a WAM, the implementation of the model is considered. We show that the implementation mainly consists of the mapping of the units onto the processing elements of the target architecture. Some performance figures of a prototype implementation on a Transputer based system are presented and discussed.