DESIGN OF CONCURRENT ERROR DETECTABLE CURRENT-MODE A/D CONVERTERS FOR REAL-TIME APPLICATIONS

被引:5
作者
WEY, CL
KRISHNAN, S
SAHLI, S
机构
[1] Department of Electrical Engineering, Michigan State University, East Lansing, 48824, MI
关键词
D O I
10.1007/BF01240680
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Analog MOS circuits are becoming increasingly sophisticated in terms of checking and correcting themselves. Self-correcting, self-compensating, or self-calibrating techniques eliminate errors traditionally associated with analog circuits. For real-time applications, however, it is rather difficult to achieve validation of the data generated from analog-to-digital (A/D) converters in the presence of faulty switching element(s). Conventionally, the validation is accomplished by using a high resolution and high accuracy D/A converter and a window comparator; i.e., the validation must highly depend on the reliability of both the D/A converter and the window comparator. In this paper, a novel current-mode A/D converter design with concurrent error detection (CED) capability is presented. The A/D converter does not need well-matched components and high-gain amplifiers. Results show that the proposed design can detect all the transient faults and most of the permanent faults. The proposed design allows users to easily switch to the normal operation mode where CED capability is not used, without causing any performance degradation.
引用
收藏
页码:65 / 74
页数:10
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