A VERTICAL SUBMICRON SIC THIN-FILM-TRANSISTOR

被引：5

作者：

HWANG, JD

FANG, YK

TSAI, TY

机构：

[1] VLSI Technology Laboratory, Electrical Engineering Department, National Cheng Kung University, Tainan, Taiwan

来源：

SOLID-STATE ELECTRONICS | 1995年 / 38卷 / 02期

关键词：

D O I：

10.1016/0038-1101(94)00120-5

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Two vertical type submicron p-channel depletion mode SIC MOSFETs have been studied. To produce the first MOSFET a SiC thin film was sputtered on a Si substrate at 600 degrees C and annealed at 1300 degrees C for 5 h in Ar atmosphere. For this MOSFET, the current-voltage characteristics of 1.6 and 0.6 mu m channel length have been investigated. In this structure, the drain characteristics show an incomplete saturation because the channel depth is too wide to be depleted. For the other MOSFET, the SiC thin film is deposited at the sidewall of the SiO2 insulator by RF sputtering at 600 degrees C, and a 0.4 mu m channel length has been developed. This MOSFET shows good saturation characteristics. Also, this device possesses a drain breakdown voltage beyond 16 V. These experimental results give the foundation for the future development of submicron SiC power integrated circuit technology.

引用

页码：275 / 278

页数：4

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