A BEHAVIORAL FAULT SIMULATOR FOR IDEAL

被引：1

作者：

KHOCHE, A ^{[1
]}

SHERLEKAR, SD ^{[1
]}

VENKATESH, G ^{[1
]}

VENKATESWARAN, R ^{[1
]}

机构：

[1] INDIAN INST TECHNOL,DEPT COMP SCI & ENGN,BOMBAY 400076,INDIA

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1992年 / 9卷 / 04期

关键词：

D O I：

10.1109/54.173327

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

[No abstract available]

引用

页码：14 / 21

页数：8

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[1]

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[3]

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[4] BEHAVIORAL-LEVEL FAULT SIMULATION [J].

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IEEE DESIGN & TEST OF COMPUTERS, 1988, 5 (03) :31-42

[5]

Ghosh S., 1991, Journal of Electronic Testing: Theory and Applications, V2, P135, DOI 10.1007/BF00133499

[6] IDEAS - A TOOL FOR VLSI CAD [J].

KUMAR, A ;

KASHYAP, V ;

SHERLEKAR, SD ;

VENKATESH, G ;

BISWAS, S ;

KUMAR, A ;

BHATT, PCP ;

KUMAR, S .

IEEE DESIGN & TEST OF COMPUTERS, 1989, 6 (05) :50-57

[7]

LIPSETT R, 1989, VHDL HARDWARE DESCRI

[8]

O'Neill M. D., 1990, Computer Hardware Description Languages and their Applications. Proceedings of the IFIP WG 10.2 Ninth International Symposium, P347

[9]

PAREKHJI RA, 1991, 4TH CSI IEEE INT S V, P187

[10]

Ward P. C., 1990, 27th ACM/IEEE Design Automation Conference. Proceedings 1990 (Cat. No.90CH2894-4), P587, DOI 10.1109/DAC.1990.114922

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