SUBSTRATE BIAS EFFECTS ON DRAIN-INDUCED BARRIER LOWERING IN SHORT-CHANNEL PMOS DEVICES

Detailed results on the substrate biasing characteristics of the drain-induced barrier lowering (DIBL) effect in short-channel PMOS devices are presented. It was found that, as the channel length decreased, the threshold voltage shift caused by DIBL first increased with increasing substrate bias and then decreased as the channel length decreased further. The channel length (LINT) corresponding to an almost zero change of the DIBL variation with substrate bias was found to be between 0.78 to 0.90 μm for our PMOS devices. This change in DIBL with substrate bias for devices with varying L can be explained as the transition of the surface DIBL effect to the subsurface DIBL effect and the onset of the punchthrough effect. Based on the experimental results, a new empirical model for describing this substrate bias characteristic of the DIBL effect is developed. Two empirical parameters, α and β are introduced, and they are linearly related to the substrate bias voltage. An analytical expression for LINT is then derived from this new model. Simulations were also carried out using the two-dimensional device numerical program MINIMOS 4.0 with the emphasis on the boron-implant channel doping profile. These simulations showed that the above two parameters, α and β are very sensitive to both the implant dose and the implant energy variation. © 1990 IEEE