TIMING-DRIVEN PARTIAL SCAN

被引：1

作者：

JOU, JY ^{[1
]}

CHENG, KT ^{[1
]}

机构：

[1] UNIV CALIF SANTA BARBARA,SANTA BARBARA,CA 93106

来源：

IEEE DESIGN & TEST OF COMPUTERS | 1995年 / 12卷 / 04期

关键词：

D O I：

10.1109/54.491238

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This partial scan approach reduces area overhead and performance degradation caused by test logic. Given an initial design that meets a target speed, the authors' algorithm selects a set of scan flip-flops that allows the circuit to meet performance requirements after the scan logic is added. if no such set exists, the algorithm selects a set that minimizes the total area increase caused by the scan logic and the subsequent performance optimization the circuit requires to meet target speed.

引用

页码：52 / 59

页数：8

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