GENERALIZED TRACE-BACK TECHNIQUES FOR SURVIVOR MEMORY MANAGEMENT IN THE VITERBI ALGORITHM

被引:26
|
作者
CYPHER, R
SHUNG, CB
机构
[1] IBM CORP, ALMADEN RES CTR, DEPT K54-802, SAN JOSE, CA 95120 USA
[2] NATL CHIAO TUNG UNIV, DEPT ELECTR ENGN, HSINCHU 300, TAIWAN
[3] NATL CHIAO TUNG UNIV, INST ELECTR, HSINCHU 300, TAIWAN
来源
JOURNAL OF VLSI SIGNAL PROCESSING | 1993年 / 5卷 / 01期
关键词
VITERBI ALGORITHM; TRACE-BACK; SURVIVOR MEMORY; VLSI AREA REQUIREMENTS;
D O I
10.1007/BF01880274
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
The trace-back technique is an effective approach for survivor memory management in the Viterbi algorithm. It is especially attractive when the number of states in the trellis is large, in which case the register exchange approach is impractical due to the area required for wiring. Previous descriptions of the trace-back technique have assumed either one or two trace-back pointers and have made specific assumptions about the speeds of those pointers. In this paper we present a general framework for implementing the trace-back technique with any number of traceback pointers and with relaxed assumptions about the speeds of the pointers. We also show that the use of additional trace-back pointers reduces the memory requirements. Two implementations of the generalized trace-back techniques based on standard RAMs and custom shift registers are presented.
引用
收藏
页码:85 / 94
页数:10
相关论文
共 24 条
  • [1] Generalized trace-back techniques for survivor memory management in the Viterbi algorithm
    Cypher, Robert
    Shung, C.Bernard
    Journal of VLSI Signal Processing Systems for Signal, Image, and Video Technology, 1993, 5 (01): : 85 - 94
  • [2] Dynamic power optimization of the trace-back process for the Viterbi algorithm
    Petrov, M
    Murgan, T
    Obeid, A
    Chitu, C
    Zipf, P
    Brakensiek, J
    Glesner, M
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS, 2004, : 721 - 724
  • [3] A VLSI DESIGN FOR A TRACE-BACK VITERBI DECODER
    TRUONG, TK
    SHIH, MT
    REED, IS
    SATORIUS, EH
    IEEE TRANSACTIONS ON COMMUNICATIONS, 1992, 40 (03) : 616 - 634
  • [4] A VLSI design for Viterbi decoder with trace-back
    Kalatchikov, AA
    SIBERIAN RUSSIAN WORKSHOPS AND TUTORIALS ON ELECTRON DEVICES AND MATERIALS, EDM 2002, VOL 2, PROCEEDINGS, 2002, : 18 - 20
  • [5] A viterbi decoder core with no trace-back unit
    Shebaita, A
    Khairy, MM
    Salama, AE
    Ashour, M
    ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 374 - 377
  • [6] A high-speed, low-power interleaved trace-back memory for Viterbi Decoder
    Israsena, Pasin
    Kale, Izzet
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS, 2006, : 2801 - 2804
  • [7] A viterbi decoder with low-power trace-back memory structure for wireless pervasive communications
    Israsena, Pasin
    Kale, Izzet
    INTERNATIONAL SYMPOSIUM ON WIRELESS PERVASIVE COMPUTING 2006, CONFERENCE PROGRAM, 2006, : 75 - +
  • [8] Survivor memory reduction in the Viterbi algorithm
    Abbasfar, A
    Yao, K
    IEEE COMMUNICATIONS LETTERS, 2005, 9 (04) : 352 - 354
  • [9] Efficient implementation of trace-back unit in a reconfigurable Viterbi decoder fabric
    Zhan, C
    Khawam, S
    Arslan, T
    Lindsay, L
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS, 2005, : 1048 - 1050
  • [10] Design of soft-output Viterbi decoders with hybrid trace-back processing
    Chang, YN
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II: COMMUNICATIONS-MULTIMEDIA SYSTEMS & APPLICATIONS, 2003, : 69 - 72