A CIRCUIT-LEVEL SIMULATION-MODEL OF PNPN DEVICES

被引：5
作者：
BRAMBILLA, A
DALLAGO, E
机构：
[1] Department of Electrical Engineering, University of Pavia
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1990年 / 9卷 / 12期
关键词：
D O I：
10.1109/43.62770
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
A numerical model of a three junction device is presented. It allows the simulation of the external characteristics of the PNPN family devices and in this work the simulation of the gate turn-off thy-ristor (GTO) is particularly considered. The authors explain the reasons that led to the realization of this new model by reviewing previous works in this area. The developed model is based upon the Ebers-Moll equations extended to include the three-junction devices and it is implemented (built-in) in the source code of the SPICE2 circuit simulator. A detailed description of the implementation of the model equations as well as different tests are reported and discussed. The obtained results are in accordance with the measurements from the devices reported on data sheets and the computation time is sufficiently short. © 1990 IEEE
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收藏
页码：1254 / 1264
页数：11
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