LOW-POWER CMOS DIGITAL DESIGN

被引：1253

作者：

CHANDRAKASAN, AP ^{[1
]}

SHENG, S ^{[1
]}

BRODERSEN, RW ^{[1
]}

机构：

[1] UNIV CALIF BERKELEY,FAC ELECT ENGN & COMP SCI,BERKELEY,CA 94720

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1992年 / 27卷 / 04期

关键词：

D O I：

10.1109/4.126534

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Motivated by emerging battery-operated applications that demand intensive computation in portable environments, techniques are investigated which reduce power consumption in CMOS digital circuits while maintaining computational throughout. Techniques for low-power operation are shown which use the lowest possible supply voltage coupled with architectural, logic style, circuit, and technology optimizations. An architectural-based scaling strategy is presented which indicates that the optimum voltage is much lower than that determined by other scaling considerations. This optimum is achieved by trading increased silicon area for reduced power consumption.

引用

页码：473 / 484

页数：12

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