A 64-CH TIME MEMORY CELL MODULE WITH A DSP AND A VME INTERFACE

被引：6

作者：

ARAI, Y

IKENO, M

机构：

[1] KEK, National Laboratory for High Energy Physics 1–1 Oho, Tsukuba, Ibaraki

来源：

IEEE TRANSACTIONS ON NUCLEAR SCIENCE | 1994年 / 41卷 / 04期

关键词：

D O I：

10.1109/23.322881

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new 64-channel Time Memory Cell (TMC) module has been developed for high-rate wire-chamber applications. A combination of the TMC chip and associated FIFO memories digitize and store input signals at 1 nsec/bit resolution for a period of 64 musec. To handle the large data size, a digital signal processor (DSP56002) is implemented in the module. The size of the module is 9U x 400 mm Euroboard size, and has a VME interface using the P1 and P2 connectors. The P3 connector has been assigned for the output of trigger signals.

引用

页码：1187 / 1191

页数：5