ARCHITECTURE OF A LADDER SOLVING PROCESSOR FOR PROGRAMMABLE CONTROLLERS

In this paper, we propose a dedicated architecture for a ladder solving processor (LSP) for programmable controllers. For this purpose, a mathematical representation of the ladder language is suggested for the first time and algorithms for solving this ladder language are presented using abstract notation. The proposed LSP is designed to be suitable for the above algorithm, and contains a logic solving unit, column execution unit and box solving unit, which employ array, pipeline and microprogrammed architectures, respectively, in order to enhance the processing speed. The performance of the proposed architecture is demonstrated by an experimental prototype of the LSP. It is also shown by computer simulation that, under reasonable assumptions, the proposed LSP can process a pure logic instruction group at 45.5 MIPS using eight cells. In the case of a ladder program, a quarter of which is a box instruction group, the LSP can process at a rate of 0.27 ms kstep-1 using a single cell architecture, and at a rate of 0.18 ms kstep-1 using four cells. This is much faster than for existing programmable controllers.