DEEP-DEPLETION-LAYER IMPACT-IONIZATION-INDUCED GATE-OXIDE BREAKDOWN IN THIN-OXIDE N-MOSFETS

被引:2
作者
HUANG, MQ
LAI, PT
MA, ZJ
WONG, H
CHENG, YC
机构
[1] CITY POLYTECH HONG KONG,DEPT ELECTR ENGN,HONG KONG,HONG KONG
[2] CITY POLYTECH HONG KONG,DIRECTORATE,HONG KONG,HONG KONG
关键词
D O I
10.1016/0038-1101(93)90196-W
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This work extensively examines gate-oxide breakdown behaviours of n-MOSFETs by means of enhancement-type and depletion-type devices with various channel dimensions under different operation conditions. The results indicate that positive-charge accumulation in gate oxide is only one of the processes occurring during high-field stress but is not the main cause for gate-oxide breakdown. The accelerated gate-oxide breakdown in MOSFETs is initiated by interface states at the Si-SiO2 interface, which are generated from the following process: holes created by impact ionization in the deep-depletion layer of the drain are injected into the gate oxide and trapped near the Si-SiO2 interface; then they recombine with hot electrons crossing the interface. In addition, gate-oxide breakdown at the gate-and-drain overlap may lead to that between gate and source.
引用
收藏
页码:1155 / 1160
页数:6
相关论文
共 31 条
[1]  
Chan T. Y., 1987, IEDM TECH DIG, P718
[2]   HOLE TRAPPING AND BREAKDOWN IN THIN SIO2 [J].
CHEN, IC ;
HOLLAND, S ;
HU, CM .
IEEE ELECTRON DEVICE LETTERS, 1986, 7 (03) :164-167
[3]  
CHEN IC, 1985, IEEE T ELECTRON DEV, V32, P413, DOI 10.1109/T-ED.1985.21957
[4]   SUB-BREAKDOWN DRAIN LEAKAGE CURRENT IN MOSFET [J].
CHEN, J ;
CHAN, TY ;
CHEN, IC ;
KO, PK ;
HU, C .
IEEE ELECTRON DEVICE LETTERS, 1987, 8 (11) :515-517
[5]   IMPACT IONIZATION MODEL FOR DIELECTRIC INSTABILITY AND BREAKDOWN [J].
DISTEFANO, TH ;
SHATZKES, M .
APPLIED PHYSICS LETTERS, 1974, 25 (12) :685-687
[6]   INTERFACE STATE CREATION AND CHARGE TRAPPING IN THE MEDIUM-TO-HIGH GATE VOLTAGE RANGE (VD/2-GREATER-THAN-OR-EQUAL-TO-VG-GREATER-THAN-OR-EQUAL-TO-VD) DURING HOT-CARRIER STRESSING OF N-MOS TRANSISTORS [J].
DOYLE, B ;
BOURCERIE, M ;
MARCHETAUX, JC ;
BOUDOU, A .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1990, 37 (03) :744-754
[7]   SURFACE CONDUCTION IN SHORT-CHANNEL MOS DEVICES AS A LIMITATION TO VLSI SCALING [J].
EITAN, B ;
FROHMANBENTCHKOWSKY, D .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1982, 29 (02) :254-266
[8]  
FENK WS, 1986, IEEE ELECTRON DEVICE, V7, P449
[10]  
Hofmann K. R., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P104