LAYER ASSIGNMENT FOR VLSI INTERCONNECT DELAY MINIMIZATION

被引：9
作者：
CIESIELSKI, MJ
机构：
来源：
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1989年 / 8卷 / 06期
关键词：
D O I：
10.1109/43.31525
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
引用
收藏
页码：702 / 707
页数：6
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