BIT-LEVEL PIPELINED DIGIT-SERIAL MULTIPLIER

被引：10
|
作者：
AGGOUN, A
ASHUR, A
IBRAHIM, MK
机构：
[1] Department of Electrical and Electronic Engineering, University of Nottingham, Nottingham
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1993年 / 75卷 / 06期
关键词：
D O I：
10.1080/00207219308907196
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new cell architecture for high performance digit-serial computation is presented. The design of this cell is based on the feed forward of the carry digit, which allows a high level of pipelining to increase the throughput rate with minimum latency. This will give designers greater flexibility in finding the best trade-off between hardware cost and throughput rate. A twin-pipe architecture to double the throughput rate of digit-serial/parallel multipliers is also presented. The effects of the number of pipelining levels and the twin architecture on the throughput rate and hardware cost are presented. A two's complement digit-serial/parallel multiplier which can operate on both negative and positive numbers is also presented.
引用
收藏
页码：1209 / 1219
页数：11
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