INTERFACE STATE CREATION AND CHARGE TRAPPING IN THE MEDIUM-TO-HIGH GATE VOLTAGE RANGE (VD/2-GREATER-THAN-OR-EQUAL-TO-VG-GREATER-THAN-OR-EQUAL-TO-VD) DURING HOT-CARRIER STRESSING OF N-MOS TRANSISTORS

An examination of the conditions of hot-carrier stressing has been carried out in detail on n-MOS transistors in order to investigate the types of damage arising from the stressing in the gate voltage range V d/2 ≥ V g ≥ V d. It has been found that although a maximum in the V, degradation is seen at V g ∗ V d/2, considerable stress damage occurs at higher gate voltages (at and around V G = V d). This stress damage obeys a different power law as a function of time to that which is seen at V g = V D/2. The examination of the damage using dynamic stress experiments and alternate static injection phases suggests that the oxide-trapped charge (N) is mostly responsible for the damage at = V d, whereas the degradation at V K = V d/2 arises from the interface state (N ss) creation. An examination of the gate current conditions shows that the oxide traps are created under conditions of maximum electronic gate current, suggesting that the hot electrons are responsible for the damage. The analysis of the time evolution of the damage suggests that the two types of damage (N ox and N ss) can be seen during a single stressing, depending on the stress voltage conditions. It is suggested that the two processes might be competitive under certain voltage conditions, and one of them is triggered at a certain finite time after the start of the stressing. It is finally shown that the damage caused by the oxide-trapped charge is less localized along the channel than the interface state creation. © 1990 IEEE