Threshold voltage control using floating back gate for ultra-thin-film SOI CMOS

With the fully depleted ultra-thin-Aim SOI CMOS, one important issue is controlling the threshold voltage (V-th) while maintaining high speed operation and low power consumption. To control the V-th, applying a bias voltage to the substrate is one of the most practical methods. We suggest a Fully depleted ultra-thin-film SOl CMOS with a floating back gate, which is formed at the lower part of the channel field inside the substrate and stores electrons injected into it. This device can eliminate the necessity of an extra circuit or a separate power supply to apply a negative voltage. The silicon wafer direct bonding technique is used to construct this device. With the prototyped devices, we can successfully control the V-th for both the nMOSFET and pMOSFET at around +/-0.5 V by controlling the quantity of the electric charges injected into the floating back gate.