VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform

This paper presents a VLSI architecture for a robust speech recognition system that enables highspeed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-mu m CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.