VLSI Architecture for Robust Speech Recognition Systems and its Implementation on a Verification Platform

被引：1

作者：

Yoshizawa, Shingo ^{[1
]}

Hayasaka, Noboru ^{[1
]}

Wada, Naoya ^{[1
]}

Miyanaga, Yoshikazu ^{[1
]}

机构：

[1] Hokkaido Univ, Grad Sch Informat Sci & Technol, Kita Ku, N-14 W-9, Sapporo, Hokkaido 0600814, Japan

来源：

JOURNAL OF ROBOTICS AND MECHATRONICS | 2005年 / 17卷 / 04期

关键词：

speech recognition; VLSI architecture; robust processing; FPGA;

D O I：

10.20965/jrm.2005.p0447

中图分类号：

TP24 [机器人技术];

学科分类号：

080202 ; 1405 ;

摘要：

This paper presents a VLSI architecture for a robust speech recognition system that enables highspeed, low-power operation. The proposed architecture improves recognition accuracy in noisy environments and realizes short-time response by implementing parallel and pipeline processing. We demonstrate improved processing time and power consumption by evaluating circuit performance in 0.25-mu m CMOS technology. We also detail a verification platform that helps users implement our hardware-based robust speech recognition system. The verification platform facilitates software conversion to hardware and promptly provides testing environments on field-programmable gate arrays.

引用

页码：447 / 455

页数：9

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