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SYSTOLIC REALIZATION OF 2-D DIGITAL-FILTERS FOR REAL-TIME IMAGE-PROCESSING
被引：0
作者：
RANK, K
UNBEHAUEN, R
机构：
[1] Univ Erlangen Nuernberg, Erlangen, Germany
来源：
关键词：
2-D Digital Filters - Minimum Cycle Time - Processing Elements (PE's) - Real-Time Image Processing - Systolic Realization;
D O I：
暂无
中图分类号：
TM [电工技术];
TN [电子技术、通信技术];
学科分类号：
0808 ;
0809 ;
摘要：
In this paper, it is shown that the 2-D 1-multiply 1-add structure, i.e. a structure with minimum cycle time introduced by Gnanasekaran [1] can be implemented without shift registers, but with a RAM-implementation of the element z1(-1) z2(+1). A systolic realization for this structure is developed which is suited for VLSI. It is shown that the systolic realization can be extended to higher order simply by adding processing elements (PEs).
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页码：258 / 261
页数：4
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