EQUIVALENCE PROOFS OF SOME YIELD MODELING METHODS FOR DEFECT-TOLERANT INTEGRATED-CIRCUITS

被引：1

作者：

THIBEAULT, C ^{[1
]}

SAVARIA, Y ^{[1
]}

HOULE, JL ^{[1
]}

机构：

[1] ECOLE POLYTECH,DEPT ELECT & COMP ENGN,MONTREAL,PQ H3C 3A7,CANADA

来源：

IEEE TRANSACTIONS ON COMPUTERS | 1995年 / 44卷 / 05期

基金：

加拿大自然科学与工程研究理事会;

关键词：

DEFECT TOLERANCE; INTEGRATED CIRCUITS; YIELD MODELING; MATHEMATICAL PROOFS; MODEL EQUIVALENCE;

D O I：

10.1109/12.381962

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, two equivalence proofs of yield modeling methods for defect-tolerant integrated circuits (ICs) are presented. These proofs are generalizations of those found in [3]; one of the proofs presented in this paper is valid for any defect-tolerant IC, while the other one is valid for defect-tolerant ICs with two levels of hierarchy.

引用

页码：724 / 728

页数：5

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