POLYCRYSTALLINE SILICON THIN-FILMS PROCESSED WITH SILICON ION-IMPLANTATION AND SUBSEQUENT SOLID-PHASE CRYSTALLIZATION - THEORY, EXPERIMENTS, AND THIN-FILM-TRANSISTOR APPLICATIONS

被引:139
作者
YAMAUCHI, N [1 ]
REIF, R [1 ]
机构
[1] MIT, DEPT ELECT ENGN & COMP SCI, CAMBRIDGE, MA 02139 USA
关键词
D O I
10.1063/1.356131
中图分类号
O59 [应用物理学];
学科分类号
摘要
A review is presented of the self-implantation method which has been developed to achieve high-quality polycrystalline silicon thin films on insulators with enhanced grain sizes and its applications to thin-film transistors (TFTs). In this method, silicon ions are implanted into an as-deposited polycrystalline silicon thin film to amorphize most of the film structure. Depending on ion implantation conditions, some seeds with <110> orientation remain in the film structure due to channeling. The film is then thermally annealed at relatively low temperatures, typically in the range of 550-700-degrees-C. With optimized process conditions, average grain sizes of 1 mum or greater can be obtained. First, an overview is given of the thin-film transistor technology which has been the greatest motivation for the research and development of the self-implantation method. Then the mechanism of selective amorphization by the silicon self-implantation and the crystallization by thermal annealing is discussed. An analytical model and experimental results are described. Polycrystalline silicon TFTs fabricated using the self-implanted polycrystalline silicon thin-films are then reviewed. The high-quality polycrystalline silicon thin films processed with the self-implantation method results in excellent TFT characteristics for both n- and p-channel devices thereby allowing complementary metal-oxide-semiconductor integrated circuits. High mobilities of around 150 cm2/V s for n-channel TFTs and around 50 cm2/V s for p-channel TFTs as well as on-to-off current ratios of 1 x 10(8) have been achieved. Fabrication and characterization of polycrystalline silicon TFTs with channel dimensions comparable to or smaller than the grain size of polycrystalline silicon films are also described to present a case study to discuss the self-implantation process and associated technologies. Finally, new approaches that extend the self-implantation method to control grain-boundary locations are discussed. If grain-boundary locations can indeed be controlled, the self-implantation method will become even more valuable in developing future high-performance TFT integrated circuits.
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页码:3235 / 3257
页数:23
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共 124 条
  • [1] A MODEL FOR POLYSILICON MOSFETS
    ANWAR, AFM
    KHONDKER, AN
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1987, 34 (06) : 1323 - 1330
  • [2] CRYSTALLIZATION OF LPCVD SILICON FILMS BY LOW-TEMPERATURE ANNEALING
    AOYAMA, T
    KAWACHI, G
    KONISHI, N
    SUZUKI, T
    OKAJIMA, Y
    MIYATA, K
    [J]. JOURNAL OF THE ELECTROCHEMICAL SOCIETY, 1989, 136 (04) : 1169 - 1173
  • [3] Blum N. A., 1972, Journal of Non-Crystalline Solids, V11, P242, DOI 10.1016/0022-3093(72)90006-3
  • [4] THE THIN-FILM TRANSISTOR - A LATE FLOWERING BLOOM
    BRODY, TP
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 1984, 31 (11) : 1614 - 1628
  • [5] STACKED CMOS SRAM CELL
    CHEN, CE
    LAM, HW
    MALHI, SDS
    PINIZZOTTO, RF
    [J]. IEEE ELECTRON DEVICE LETTERS, 1983, 4 (08) : 272 - 274
  • [6] SINGLE-TRANSISTOR LATCH IN SOI MOSFETS
    CHEN, CED
    MATLOUBIAN, M
    SUNDARESAN, R
    MAO, BY
    WEI, CC
    POLLACK, GP
    [J]. IEEE ELECTRON DEVICE LETTERS, 1988, 9 (12) : 636 - 638
  • [7] AN APPLICATION OF THE BOLTZMANN TRANSPORT-EQUATION TO ION RANGE AND DAMAGE DISTRIBUTIONS IN MULTILAYERED TARGETS
    CHRISTEL, LA
    GIBBONS, JF
    MYLROIE, S
    [J]. JOURNAL OF APPLIED PHYSICS, 1980, 51 (12) : 6176 - 6182
  • [8] SUBSTRATE-ORIENTATION DEPENDENCE OF EPITAXIAL REGROWTH RATE FROM SI-IMPLANTED AMORPHOUS SIA
    CSEPREGI, L
    KENNEDY, EF
    MAYER, JW
    SIGMON, TW
    [J]. JOURNAL OF APPLIED PHYSICS, 1978, 49 (07) : 3906 - 3911
  • [9] IMPROVED SUBTHRESHOLD CHARACTERISTICS OF N-CHANNEL SOI TRANSISTORS
    DAVIS, JR
    GLACCUM, AE
    REESON, K
    HEMMENT, PLF
    [J]. IEEE ELECTRON DEVICE LETTERS, 1986, 7 (10) : 570 - 572
  • [10] DESMET H, 1992, OCT P JAP DISPL HIR, P225