A NEW TESTING METHOD FOR EEPLA

被引：4

作者：

RAJSUMAN, R ^{[1
]}

机构：

[1] CASE WESTERN RESERVE UNIV,DEPT ELECT ENGN & APPL PHYS,CLEVELAND,OH 44106

来源：

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 1994年 / 13卷 / 07期

关键词：

D O I：

10.1109/43.293950

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A testing method for EEPLA's is presented. The method requires small amount of extra hardware and provides complete fault coverage. This method exploits the fact that each crosspoint can be reprogrammed in EEPLA. To our knowledge, this is the first algorithmic test method applicable to EEPLA's. In the proposed approach, all single and multiple crosspoint faults, stuck-at faults, and bridging faults are detectable. The test set is simple and is easy to derive.

引用

页码：935 / 939

页数：5

共 20 条

[1] FAULT-TOLERANT 64K DYNAMIC RANDOM-ACCESS MEMORY [J].

CENKER, RP ;

CLEMONS, DG ;

HUBER, WR ;

PETRIZZI, JB ;

PROCYK, FJ ;

TROUT, GM .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1979, 26 (06) :853-860

[2]

FUJIWARA H, 1981, IEEE T COMPUT, V30, P823, DOI 10.1109/TC.1981.1675712

[3]

FUJIWARA H, 1985, 15TH P INT S FAULT T, P112

[4]

Hong S. J., 1980, 10th International Symposium on Fault-Tolerant Computing, P131

[5]

KHAKBAZ J, 1983, 13TH P INT S FAULT T, P426

[6]

LALA PK, 1990, PLD DIGITAL SYSTEM D

[7]

LIGHTHART MM, 1989, P EUROPEAN TEST C, P252

[8] DESIGN OF LARGE EMBEDDED CMOS PLAS FOR BUILT-IN SELF-TEST [J].

LIU, DL ;

MCCLUSKEY, EJ .

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1988, 7 (01) :50-59

[9]

Malaiya Y. K., 1986, Proceedings of the IEEE International Conference on Computer Design: VLSI in Computers. ICCD '86 (Cat. No.86CH2348-1), P78

[10]

Maly W., 1987, 24th ACM/IEEE Design Automation Conference Proceedings 1987, P173, DOI 10.1145/37888.37914

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