IMPLEMENTATION OF MICROPIPELINES IN ENABLE DISABLE CMOS DIFFERENTIAL LOGIC

This paper examines an alternative implementation of Micropipelines' logic/data processing structures. To satisfy the timing requirements of the Micropipeline, currently a delay element needs to be introduced in each of its stages. The alternative approach presented here eliminates this by using a differential CMOS logic family-Enable/Disable CMOS differential logic, ECDL instead of the conventional static CMOS. This will ease the process of synthesizing Micropipeline stages. The effectiveness of this technique in eliminating the delay requirement has been exemplified by presenting an adder implemented using ECDL.