Fundus image denoising using FPGA hardware architecture

被引:12
作者
Fredj, Amira Hadj [1 ]
Ben Abdallah, Mariem [1 ]
Malek, Jihene [1 ]
Azar, Ahmad Taher [2 ]
机构
[1] Monastir Univ, Elect & Microelect Lab, Monastir, Tunisia
[2] Benha Univ, Fac Comp & Informat, Banha, Egypt
关键词
SRAD filter; FPGA; field-programmable gate array; parallel architecture; retinal fundus image;
D O I
10.1504/IJCAT.2016.077791
中图分类号
TP39 [计算机的应用];
学科分类号
081203 ; 0835 ;
摘要
Image processing algorithms, implemented in hardware, have recently emerged as the most viable solution for improving the performance of image processing systems. In this paper, a version of an anisotropic diffusion technique is used to reduce noise from retinal images, namely Speckle Reducing Anisotropic Diffusion ( SRAD). The SRAD filter can improve images corrupted by multiplicative or additive noise, but it has been the most computationally complex and it has not been suitable for software implementation in real-time processing. In this paper, an efficient Field-Programmable Gate Array ( FPGA)-based implementation of the SRAD filter is presented to accelerate the processing time. A comparison of the most used classical suppression filters like Gaussian, Median, Perona and Malik anisotropic diffusion has been carried out. The experimental results reveal a 38x performance improvement over the original MATLAB implementation and a 1.33x performance improvement over the hardware implementation using the Xilinx System Generator tool.
引用
收藏
页码:1 / 13
页数:13
相关论文
共 50 条
  • [21] Efficient BinDCT hardware architecture exploration and implementation on FPGA
    Ben Abdelali, Abdessalem
    Chatti, Ichraf
    Hannachi, Marwa
    Mtibaa, Abdellatif
    JOURNAL OF ADVANCED RESEARCH, 2016, 7 (06) : 909 - 922
  • [22] An FPGA Design for Real-Time Image Denoising
    Ben Atitallah, Ahmed
    COMPUTER SYSTEMS SCIENCE AND ENGINEERING, 2022, 43 (02): : 803 - 816
  • [23] The FPGA Hardware Implementation of the Gated Recurrent Unit Architecture
    Zaghloul, Zaghloul Saad
    Elsayed, Nelly
    SOUTHEASTCON 2021, 2021, : 366 - 370
  • [24] Towards a general framework for FPGA based image processing using hardware skeletons
    Benkrid, K
    Crookes, D
    Benkrid, A
    PARALLEL COMPUTING, 2002, 28 (7-8) : 1141 - 1154
  • [25] A dedicated hardware architecture for real-time auto-focusing using an FPGA
    Jin, Seunghun
    Cho, Junguk
    Kwon, Key Ho
    Jeon, Jae Wook
    MACHINE VISION AND APPLICATIONS, 2010, 21 (05) : 727 - 734
  • [26] A dedicated hardware architecture for real-time auto-focusing using an FPGA
    Seunghun Jin
    Junguk Cho
    Key Ho Kwon
    Jae Wook Jeon
    Machine Vision and Applications, 2010, 21 : 727 - 734
  • [27] Pipelined Hardware Architecture for High-Speed Optical Flow Estimation using FPGA
    Jin, Seunghun
    Kim, Dongkyun
    Dung Duc Nguyen
    Jeon, Jae Wook
    2010 18TH IEEE ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2010), 2010, : 33 - 36
  • [28] A compact hardware architecture for digital image stabilization using integral projections
    Araneda, Luis
    Figueroa, Miguel
    MICROPROCESSORS AND MICROSYSTEMS, 2015, 39 (08) : 987 - 997
  • [29] Hardware based image processing library for Virtex FPGA
    Gorgon, M
    Tadeusiewicz, R
    RECONFIGURABLE TECHNOLOGY: FPGAS FOR COMPUTING AND APPLICATIONS II, 2000, 4212 : 1 - 10
  • [30] A hardware/software architecture dedicated to model predictive control law and implemented into an FPGA platform
    Sirine, Telmoudi Brini
    Badreddine, Bouzouita
    Faouzi, Bouani
    INTERNATIONAL JOURNAL OF AUTOMATION AND CONTROL, 2019, 13 (03) : 301 - 323