PARAMETRIC FORMULATION OF CMOS LATCH-UP AS A FUNCTION OF CHIP LAYOUT PARAMETERS

被引：3
作者：
LOHIA, R
ALI, A
机构：
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1988年 / 23卷 / 01期
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D O I：
10.1109/4.285
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
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页码：245 / 250
页数：6
相关论文
共 13 条
[1]  
CLAUDIUS G, 1985, SEMICONDUCTOR IN SEP, P180
[2]  
CLAUDIUS G, 1985, 4TH P ANN EXP TEST M, P722
[3]  
ESTREICH DB, 1980, G2019 STANF U STANF
[4]   A CMOS STRUCTURE WITH HIGH LATCHUP HOLDING VOLTAGE [J].
HU, GJ ;
BRUCE, RH .
IEEE ELECTRON DEVICE LETTERS, 1984, 5 (06) :211-214
[5]  
IIZUKA T, 1981, MAY CMOS WORKSH SAN
[6]   DC HOLDING AND DYNAMIC TRIGGERING CHARACTERISTICS OF BULK CMOS LATCHUP [J].
RUNG, RD ;
MOMOSE, H .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 1983, 30 (12) :1647-1655
[7]  
SCHEIBER SF, 1985, TEST MEASUREMENT MAY, P71
[8]  
Taur Y., 1984, International Electron Devices Meeting. Technical Digest (Cat. No. 84CH2099-0), P398
[9]  
TROUTMAN RR, 1986, LATCH UP CMOS TECHNO
[10]  
TROUTMAN RR, 1983, IEEE ELECTRON DEVICE, V4
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