A TRANSPUTER-BASED GATE-LEVEL FAULT SIMULATOR

被引：0

作者：

CABODI, G ^{[1
]}

GAI, S ^{[1
]}

REORDA, MS ^{[1
]}

机构：

[1] POLITECN TORINO, CNR, CTR ELABORAZIONE NUMERALE SEGNALI, I-10129 TURIN, ITALY

来源：

MICROPROCESSING AND MICROPROGRAMMING | 1990年 / 30卷 / 1-5期

关键词：

D O I：

10.1016/0165-6074(90)90294-J

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Fault simulating digital devices requires powerful tools able to deal with their increased size and complexity. Software simulators are often unable to satisfy the needs of designers and test engineers and hardware accelerators have been proposed to solve the problem. We present a system running on a net of transputers using a fault-partitioning strategy to fully exploit the available processors. The results show that this solution can represent a good trade-off between the cost of the system and the obtained speed-up. © 1989.

引用

页码：529 / 534

页数：6

共 15 条

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