A WAFER-SCALE-LEVEL SYSTEM INTEGRATED LSI CONTAINING 11 4-MB DRAMS, 6 64-KB SRAMS, AND AN 18K-GATE ARRAY

As DRAM capacity and density increase, DRAM is becoming more than a simple large-capacity memory; it is evolving into an application-specific memory system containing control logic or a high-speed cache memory. This paper describes a system integrated LSI chip (SLSI) that contains eleven 4-Mb DRAM's, six 64-kb SRAM's, and an 18K-gate array, for a graphics application system. To implement the SLSI on a silicon chip, three new key techniques are developed: 1) system redundancy for defect relief, 2) chip configuration and fabrication with blade masking to achieve a hybrid 38.16 x 50.4-mm2 chip, and 3) large-capability and high-reliability 324-pin 54 x 86-mm2 plastic pin grid array package. Using a system redundancy technique, a 60% yield for the SLSI is achieved with a 40% yield for the DRAM itself. That is twice the 30% yield of the conventional repair scheme. Access times are 65 ns for the DRAM and 14 ns for the SRAM, with a 3.9-W chip power dissipation.