SIMD-SYSTOLIC ARCHITECTURE AND VLSI CHIP FOR COMPUTING THE DYNAMIC TIME-WARPING ALGORITHM

被引：1
|
作者：
WU, CM
YAN, MS
机构：
[1] Department of Electronic Engineering, National Taiwan Institute of Technology, Taipei, 43, Keelung Road, Sec. 4, Taiwan
来源：
INTERNATIONAL JOURNAL OF ELECTRONICS | 1993年 / 75卷 / 04期
关键词：
D O I：
10.1080/00207219308907151
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A VLSI architecture, which exhibits both SIMD and systolic behaviour for computing the dynamic time-warping (DTW) algorithm is presented. Such an architecture is well-suited for VLSI implementation because of its regular structure and small number of input/output. Currently, based on a 1.2 mum CMOS technology, a SIMD-systolic data-path chip has been designed and fabricated for computing the DTW algorithm. It is functionally correct and packaged as a 68-pin PGA chip. With such a chip, a 20000-word real-time DTW-based speech recognition system is achievable.
引用
收藏
页码：731 / 741
页数：11
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