MIXMOS - A MIXED-LEVEL SIMULATOR FOR DIGITAL MOS CIRCUITS USING A NEW ALGEBRAIC APPROACH

被引:0
|
作者
KONG, JH
SZYGENDA, SA
机构
[1] Electrical and Computer Engineering Department, The University of Texas at Austin, Austin
关键词
ELECTRONIC DESIGN AUTOMATION; SILICON DESIGN; DIGITAL LOGIC SIMULATION; MIXED-LEVEL SIMULATION;
D O I
10.1016/0010-4485(90)90009-2
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
The paper presents a new mixed-level simulation tool for digital VLSI circuits implemented in MOS technology. A digital circuit is described as an interconnection of gate-and switch-level models. A new algebraic structure, comprised of algebras for the gate and switch levels, is developed to achieve consistency and accuracy between the two different levels of abstraction. Based on these algebras two evaluation algorithms - one for the gate level and the other for the switch level - are developed to handle Boolean expressions and switch-level descriptions, with the strength capability that is usually needed to simulate MOS circuits. The combination of the two algorithms results in a mixed-level MOS simulator, MixMOS, which achieves switch-level accuracy with performance that approaches that achieved by gate-level simulators.
引用
收藏
页码:618 / 632
页数:15
相关论文
共 50 条
  • [31] Logi-Thermal Analysis of Digital Circuits Using Mixed-Signal Simulator Questa ADMS
    Petrosyants, K. O.
    Rjabov, N. I.
    PROCEEDINGS OF IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2013), 2013,
  • [32] Increase of Trichoderma harzianum Production Using Mixed-Level Fractional Factorial Design
    Yanez-Hernandez, Oscar
    Rios-Lira, Armando
    Verenice Pantoja-Pacheco, Yaquelin
    Alfredo Jimenez-Garcia, Jose
    Antonio Vazquez-Lopez, Jose
    Hernandez-Gonzalez, Salvador
    APPLIED SCIENCES-BASEL, 2023, 13 (16):
  • [33] PERFORMANCE-ORIENTED SCALING LAWS FOR MIXED ANALOG DIGITAL MOS CIRCUITS
    SINGH, R
    BHATTACHARYYA, AB
    SOLID-STATE ELECTRONICS, 1989, 32 (10) : 835 - 838
  • [34] Concurrent logic and interconnect delay estimation of MOS circuits by mixed, algebraic and Boolean symbolic analysis
    Bhattacharya, S
    Shi, CJR
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV: DIGITAL SIGNAL PROCESSING-COMPUTER AIDED NETWORK DESIGN-ADVANCED TECHNOLOGY, 2003, : 660 - 663
  • [35] Two-dimensional mixed-level device and circuit simulation using HSPICE
    Natl Central Univ, Chung-Li, Taiwan
    Proc Natl Sci Counc Repub China Part A Phys Sci Eng, 2 (290-296):
  • [36] Dual-Purpose Mixed-Level Test Generation Using Swarm Intelligence
    Gent, Kelson
    Hsiao, Michael S.
    2014 IEEE 23RD ASIAN TEST SYMPOSIUM (ATS), 2014, : 230 - 235
  • [37] A new description of MOS circuits at switch-level with applications
    Pedram, M
    Wu, XW
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 1997, E80A (10) : 1892 - 1901
  • [38] A new evolvable hardware approach to digital circuits using cultural algorithms
    Pan, Zhongliang
    Chen, Ling
    Zhang, Guangzhao
    DYNAMICS OF CONTINUOUS DISCRETE AND IMPULSIVE SYSTEMS-SERIES B-APPLICATIONS & ALGORITHMS, 2007, 14 : 781 - 785
  • [39] RELAX - A NEW CIRCUIT SIMULATOR FOR LARGE-SCALE MOS INTEGRATED-CIRCUITS
    LELARASMEE, E
    SANGIOVANNIVINCENTELLI, A
    COMPUTER-AIDED DESIGN, 1983, 15 (05) : 262 - 270
  • [40] Reduced-order modeling of capacitive MEMS microphones using mixed-level simulation
    Niessner, M.
    Bedyk, W.
    Schrag, G.
    Wachutka, G.
    Margesin, B.
    Faes, A.
    ASDAM '06: SIXTH INTERNATIONAL CONFERENCE ON ADVANCED SEMICONDUCTOR DEVICES AND MICROSYSTEMS, CONFERENCE PROCEEDINGS, 2006, : 283 - 286