TECHNIQUES FOR AREA ESTIMATION OF VLSI LAYOUTS

被引：26

作者：

KURDAHI, FJ ^{[1
]}

PARKER, AC ^{[1
]}

机构：

[1] UNIV CALIF LOS ANGELES,DEPT ELECT ENGN,LOS ANGELES,CA 90024

来源：

关键词：

D O I：

10.1109/43.21821

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

引用

页码：81 / 92

页数：12

共 17 条

[1] ELGAMAL AA, 1981, IEEE T CIRCUITS SYST, V28, P127, DOI 10.1109/TCS.1981.1084958
[2] FELLER A, 1978, AFIPS C P, V47, P303
[3] FEUER M, 1982, IEEE T COMPUT, V31, P29, DOI 10.1109/TC.1982.1675882
[4] GRANACKI J, 1983, 20TH IEEE ACM P DES, P419
[5] Hafer L. J., 1983, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, VCAD-2, P4, DOI 10.1109/TCAD.1983.1270016
[6] HELLER WR, 1978, J DES AUTOM FAULT, V2, P117
[7] HELLER WR, 1977, 14TH IEEE ACM P DES, P20
[8] KANG S, 1983, 20TH P DES AUT C, P457
[9] KURDAHI FJ, 1987, THESIS U SO CALIFORN
[10] PIN VERSUS BLOCK RELATIONSHIP FOR PARTITIONS OF LOGIC GRAPHS
LANDMAN, BS
RUSSO, RL
[J]. IEEE TRANSACTIONS ON COMPUTERS, 1971, C 20 (12) : 1469 - &