FOLDED SOURCE-COUPLED LOGIC VS CMOS STATIC LOGIC FOR LOW-NOISE MIXED-SIGNAL ICS

CMOS folded source-coupled logic (FSCL) uses a smaller logic voltage swing (Delta V-L congruent to 0.2V(dd)) than conventional static logic and achieves a smaller power-delay product at high operating frequencies. By using current-steering techniques in fully-differential FSCL circuits to maintain a constant power supply current, digital switching noise is reduced by 30-300 times compared to conventional CMOS static logic. Measured results are presented for FSCL gates fabricated in a 2-mu m CMOS process, and simulated results with a standard 1-mu m process are used to compre the power, delay, and switching noise characteristics of FSCL and static logic with 5.0-, 3.3-, and 2.0-V power supplies.