A BICMOS LOW-POWER CURRENT-MODE GATE

被引：5
|
作者：
EMBABI, SHK
BRUESKE, DE
RACHAMREDDY, K
机构：
[1] Texas A&M Univ, College Station, TX
来源：
IEEE JOURNAL OF SOLID-STATE CIRCUITS | 1994年 / 29卷 / 06期
关键词：
Logic gates;
D O I：
10.1109/4.293123
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A controllable BiCMOS low-power current mode logic (LPCML) gate is proposed. The LPCML can be controlled to operate in a high-power mode when its inputs and outputs are in transition. When the gate is idle, it is in a low-power mode and the circuit maintains its output levels with very little tail current. A circuit implementation of the LPCML is also reported with a discussion on its design considerations. A circuit implementation of the LPCML with conventional CML indicates that its delay is greater than that of CML by about 60%. The power consumption of LPCML is proportional to the time it spends in the high-power mode, and, hence, may be significantly lower than that of CML.
引用
收藏
页码：741 / 745
页数：5
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